1. Technical Field of the Invention
The present invention relates to a method of manufacturing an SiC single crystal wafer.
2. Description of the Related Art
SiC single crystals have a wider bandgap than Si or GaAs single crystals and exhibits a great dielectric strength and a high thermal conductivity. These properties are effectively applicable to making a semiconductor device operating at a high temperature or a power semiconductor device with a high breakdown voltage. Thus, to realize a semiconductor device that can exhibit outstanding characteristics that have never been achieved by any conventional semiconductor such as silicon, semiconductor devices of SiC single crystals have been researched and developed extensively. SiC single crystals grown by a conventional technique would often have unsatisfactory crystal quality. That is why a semiconductor device used to be fabricated on an SiC epitaxial layer grown on a wafer consisting essentially of SiC single crystals. Recently, however, SiC single crystals of quality can sometimes be obtained, and a method of fabricating a semiconductor device directly on an SiC wafer also started being researched.
Meanwhile, GaN based semiconductor devices that emit an ultraviolet ray or a blue ray have also been researched as a light source for reading and writing information from/on an optical storage medium at a high density, presenting an image, or providing general illumination. However, it is usually difficult to grow a GaN based semiconductor to the shape of a big single crystal ingot with few crystal defects. That is why a technique of epitaxially growing a GaN based semiconductor layer on an SiC single crystal wafer is now an object of a lot of attention in the art.
For that purpose, an SiC single crystal wafer with a flat and non-warped surface having no flaws is in high demand. The present inventor proposed a technique of making a flat SiC wafer by removing processing stress in a Japanese patent application that has not been laid open yet.
On the other hand, a chemical mechanical polishing (CMP) process has been used often as a typical technique of planarizing the surface of an SiC wafer. However, SiC is the second hardest material after diamond, and therefore, cannot be planarized at a sufficiently high polishing rate by the CMP process, resulting in poor processing efficiency. To increase the polishing rate, there is known a method of performing a CMP process with high pressure applied to an SiC wafer. In that case, an affected layer could be easily produced deep inside the SiC wafer.
To overcome these problems, Patent Document No. 1 discloses a method of planarizing the surface of an SiC wafer by using a reactive etching and a water vapor oxidation in combination. More specifically, according to that method, the surface of an SiC wafer is mirror-polished mechanically, cleaned with organic and inorganic liquids, and then subjected to a reactive etching process. In this manner, a damage layer is removed uniformly with the surface kept sufficiently planar. Thereafter, the surface of the wafer is oxidized with water vapor and then the resultant oxide layer is removed with hydrofluoric acid.
Patent Document No. 2 discloses a process in which an affected layer is removed from the surface of an SiC wafer by a first reactive etching process using Ar, for example, and then an ion bombardment damage layer, produced in a surface area of the wafer as a result of the first reactive etching process, is removed by another reactive etching process using CF4 and O2.
Also, Non-patent Document No. 1 reports that the processing efficiency can be improved by oxidizing the surface of an SiC wafer with water vapor and then subjecting the wafer to a CMP process.
However, in the reactive ion etching processes adopted in these conventional methods, the etching action advances almost without altering the original surface shape. Accordingly, if the surface of the wafer has flaws, then those flaws cannot be flattened out completely even through the reactive etching process. In addition, in a reactive ion etching process, the wafer is bombarded with accelerated radical species, and it is difficult to fully repair the damage caused on the wafer. The process in which an oxide layer is formed by water vapor oxidation and then removed is not practical, either, because the SiC wafer needs to be exposed to water vapor for a long time while being kept heated to a high temperature.
That is why it is difficult to planarize the surface of the wafer and remove the damage layer from the wafer surface completely according to the methods disclosed in Patent Documents Nos. 1 and 2. In the method disclosed in Non-patent Document No. 1, the polishing process can be finished in a shorter time than a method by which the surface of the SiC wafer is planarized only by a CMP process. Even so, it still takes about three hours to get the oxidation process done and about two hours to finish the polishing process according to the method disclosed in Non-patent Document No. 1, which is also far from being actually usable. In addition, it is hard to eliminate the flaws from the wafer surface completely, too.                Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 6-188163        Patent Document No. 2: Japanese Patent Application Laid-Open Publication No. 9-183700        Non-patent Document No. 1: Sinnittetsu Giho (Nippon Steel Technical Report) Vol. 374, pp. 32-36        